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? semiconductor msm54c864 1/33 ? semiconductor msm54c864 65,536-word 8-bit multiport dram description the msm54c864 is a 512kbit cmos multiport memory composed of a 65,536-word by 8-bit dynamic random access memory, ram port, and a 256-word by 8-bit static serial access memory, sam port. the ram port and sam port operate independently and asynchronously. the msm54c864 supports three types of operation : random access to and from the ram port, high speed serial access to and from the sam port and bidirectional transfer of data between any selected row in the ram port and the sam port. the ram port and the sam port can be accessed independently except when data is being transferred between them internally. features ? single power supply of 5 v 10% with a built-in v bb generator ? all inputs and outputs: ttl compatible ? multiport organization ram port: 64k word 8 bits sam port: 256 word 8 bits ? ram port fast page mode, read-modify-write cas before ras refresh, hidden refresh ras only refresh, standard write-per-bit ? sam port high speed serial read / write capability fully static register 256 tap location ? ram-sam bidirectional, read / write / pseudo write, real time read transfer ? refresh : 256 cycles/4 ms ? package options: 40-pin 475 mil plastic zip (zip40-p-475-1.27) (product : msm54c864-xxzs) 40-pin 400 mil plastic soj (soj40-p-400-1.27) (product : msm54c864-xxjs) xx indicates speed rank. product family msm54c864-70 msm54c864-80 msm54c864-10 access time ram sam 70 ns 25 ns 80 ns 25 ns 100 ns 25 ns cycle time ram sam 140 ns 30 ns 150 ns 30 ns 180 ns 30 ns power dissipation operating 120 ma 110 ma 100 ma standby 8 ma 8 ma 8 ma family e2l0010-17-y1 this version: jan. 1998 previous version: dec. 1996
? semiconductor msm54c864 2/33 pin configuration (top view) w5/io5 w7/io7 se sio6 sio8 sc sio2 sio4 w1/io1 w3/io3 w4/io4 wb / we nc v ss2 a5 nc a7 a2 a0 cas w6/io6 w8/io8 sio5 sio7 v ss1 sio1 sio3 dt / oe w2/io2 v ss3 v cc1 ras a6 nc a4 v cc2 a3 a1 nc nc sc sio1 sio2 sio3 sio4 dt / oe w1/io1 w2/io2 w3/io3 w4/io4 v cc1 wb / we nc ras nc nc a6 a5 a4 v cc2 v ss1 sio8 sio7 sio6 sio5 se w8/io8 w7/io7 w6/io6 w5/io5 v ss2 nc nc cas nc a0 a1 a2 a3 a7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 40-pin plastic soj 40-pin plastic zip a0 - a7 address input ras row address strobe cas column address strobe dt / oe data transfer / output enable wb / we write per bit / write enable w1/io1 - w8/io8 write mask / data in, out sc serial clock se serial enable sio1 - sio8 serial input / output v cc / v ss power supply (5 v) / ground (0 v) nc no connection pin name function note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin.
? semiconductor msm54c864 3/33 block diagram i/o buffer (ram) timing generator write control write per bit control mask register (8 bit) column decoder sence amplifier row decoder serial address counter column address buffer row address buffer refresh counter i/o buffer (sam) w1/io1 - w8/io8 sio1 - sio8 v cc v ss a0 - a7 sam ras cas dt / oe wb / we sc se selecter 256 256 8 cell array
? semiconductor msm54c864 4/33 electrical characteristics absolute maximum ratings parameter symbol condition rating unit input output voltage v t ta = 25c C1.0 to 7.0 v output current l os ta = 25c 50 ma power dissipation p d ta = 25c 1 w operating temperature t opr 0 to 70 c storage temperature t stg C55 to 150 c (note : 16) recommended operating conditions parameter symbol unit power supply voltage v cc v input high voltage v ih v input low voltage v il v min. 4.5 2.4 C1.0 typ. 5.0 max. 5.5 6.5 0.8 (ta = 0c to 70c) (note : 17) capacitance parameter symbol unit input capacitance c i pf input / output capacitance c i/o pf min. max. 7 9 (v cc = 5 v 10%, f = 1 mhz, ta = 25c) note : this parameter is periodically sampled and is not 100% tested. dc characteristics 1 parameter output "h" level voltage output "l" level voltage input leakage current output leakage current symbol v oh v ol i li i lo condition i oh = C2 ma i ol = 2 ma 0 v in v cc all other pins not under test = 0 v 0 v out 5.5 v output disable min. max. 2.4 C10 C10 0.4 10 10 v m a unit
? semiconductor msm54c864 5/33 dc characteristics 2 -70 -80 -10 unit note symbol item (ram) sam max. max. max. 85 75 65 ma 1, 2 i cc1 operating current standby 120 110 100 1, 2 ( ras , cas cycling, t rc = t rc min.) active 888 standby current 50 45 40 1, 2 ( ras , cas = v ih ) 85 75 65 1, 2 ras only refresh current 120 110 100 1, 2 ( ras cycling, cas = v ih , t rc = t rc min.) 70 65 60 1, 2 page mode current 120 110 100 1, 2 ( ras = v il , cas cycling, t pc = t pc min.) 85 75 65 1, 2 cas before ras refresh current 120 110 100 1, 2 ( ras cycling, cas before ras , t rc = t rc min.) 85 75 65 1, 2 data transfer current 120 110 100 1, 2 ( ras , cas cycling, t rc = t rc min.) i cc1a i cc2 i cc2a i cc3 i cc3a i cc4 i cc4a i cc5 i cc5a i cc6 i cc6a standby active standby active standby active standby active standby active (v cc = 5 v 10%, ta = 0c to 70c) 3
? semiconductor msm54c864 6/33 ac characteristics (1/3) parameter symbol note unit ns 180 150 140 ns 50 40 35 ns 25 25 20 ns 50 45 40 ns 35 3 35 3 35 3 ns 100k 100 100k 80 100k 70 t rc t prwc t aa t cac t cpa t rasp t cas t rcd max. min. max. min. max. min. -10 -80 -70 ns 100 90 90 ns 10k 25 10k 25 10k 20 13 20 20 20 ns 55 50 45 t pc t rac ns 100 80 70 9 ns 20 0 20 0 20 0 t off ns 70 60 60 ns 25 25 20 t rsh ns 100 80 70 t csh t t t rp ns 10k 100 10k 80 10k 70 t ras t rad 13 20 15 15 t asr 0 0 0 t rah 10 10 10 t asc 0 0 0 t cah 15 15 15 t ar 70 55 55 t rcs 0 0 0 t rch 10 0 0 0 t rrh 10 0 0 0 t wch 15 15 15 t wcr 70 55 55 t wp 15 15 15 t rwl 25 20 20 t cwl 25 20 20 7, 13 7, 14 7, 14 7, 13 6 ns 75 55 50 ns 50 40 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 235 195 195 t rwc t ral t crp ns 55 40 35 10 10 10 t cp 10 10 10 ns ns access time from column address column address hold time referenced to ras column address set-up time row address set-up time access time from cas column address hold time cas pulse width cas precharge time (fast page mode) access time from cas precharge cas to ras precharge time cas hold time write command to cas lead time output buffer turn-off delay fast page mode cycle time fast page mode read modify write cycle time row address hold time ras pulse width (fast page mode only) random read or write cycle time ras to cas delay time read command hold time read command set-up time read modify write cycle time ras precharge time read command hold time referenced to ras write command to ras lead time access time from ras ras to column address delay time column address to ras lead time ras pulse width ras hold time transition time (rise and fall) write command hold time referenced to ras write command pulse width write command hold time t cpn 10 10 10 ns cas precharge time (v cc = 5 v 10%, ta = 0c to 70c) note 4, 5, 6
? semiconductor msm54c864 7/33 ac characteristics (2/3) parameter symbol note unit ns 55 45 45 ns 0 0 0 ns 0 0 0 ns 20 0 10 0 10 0 ns 10 10 10 t rwd t cwd t dzc t dzo t csr t ref t wsr max. min. max. min. max. min. -10 -80 -70 ns 130 100 100 ms 4 4 4 0 0 0 t awd ns 80 65 65 ns 25 20 20 t oea ns 20 10 10 ns 10 10 10 t chr ns 0 0 0 t rpc t oez t oeh ns 15 15 15 t roh t rwh 15 15 15 t ms 0 0 0 t mh 15 15 15 t ths 0 0 0 t thh 15 15 15 t tls 0 0 0 t tlh 15 15 15 t trp 70 60 60 t tp 30 20 20 t rsd 100 80 70 t asd 50 45 45 t csd 25 25 20 t tsl 5 5 5 12 12 ns ns ns ns ns ns ns ns 10k 10k 10k ns ns ns ns ns ns t rth 80 65 60 ns 10k 10k 10k t ath 30 30 25 ns t cth 25 25 20 ns t esr t reh ns 0 0 0 15 15 15 ns 12 column address to first sc delay time (read transfer) column address to we delay time cas hold time for cas before ras cycle cas set-up time for cas before ras cycle cas to we delay time data to cas delay time data to oe delay time se set-up time referenced to ras write per bit mask data hold time write per bit mask data set-up time oe command hold time refresh period se hold time referenced to ras ras hold time referenced to oe ras precharge to cas active time ras to we delay time wb hold time access time from oe ras to first sc delay time (read transfer) dt to ras precharge time wb set-up time last sc to dt lead time (real time read transfer) output buffer turn-off delay from oe dt low hold time referenced to column address (real time read transfer) dt low hold time referenced to cas (real time read transfer) dt precharge time dt high hold time dt high set-up time dt low hold time dt low set-up time dt low hold time referenced to ras (real time read transfer) cas to first sc delay time (read transfer) ns 0 0 0 t ds ns 70 55 55 t dhr ns 15 15 15 t dh 11 11 data hold time data hold time referenced to ras data set-up time t wcs 0 0 0ns write command set-up time 12 ns 20 10 10 t oed oe to data delay time (v cc = 5 v 10%, ta = 0c to 70c) note 4, 5, 6 9 7
? semiconductor msm54c864 8/33 ac characteristics (3/3) parameter symbol note unit ns 10 10 10 ns 25 25 25 ns 5 5 5 ns 25 25 25 t scc t scp t sca t soh max. min. max. min. max. min. -10 -80 -70 ns 30 30 30 t sc ns 10 10 10 8 ns 25 25 25 t sea ns 25 25 25 t se t sep ns 20 0 20 0 20 0 t sez t srd t sze 0 0 0 t szs 0 0 0 t sws 5 5 5 t swh 15 15 15 t swis 5 5 5 t swih 15 15 15 8 9 ns ns ns ns ns ns ns t sdd ns 50 40 40 access time from sc sc pulse width (sc high time) sc cycle time sc precharge time (sc low time) ras to serial input delay time se pulse width access time from se se precharge time serial write disable hold time serial write disable set-up time serial write enable set-up time serial input to se delay time serial input to first sc delay time serial output buffer turn-off delay from se serial output hold time from sc serial write enable hold time 25 20 20 ras to first sc delay time (serial input) ns 15 15 15 t tsd ns 50 10 40 10 40 10 t sdz ns 30 25 25 t srs 9 serial output buffer turn-off delay from ras (pseudo write transfer) dt to first sc delay time (read transfer) last sc to ras set-up time (serial input) (v cc = 5 v 10%, ta = 0c to 70c) note 4, 5, 6 t sds 0 0 0 t sdh 15 15 15 ns ns serial input hold time serial input set-up time
? semiconductor msm54c864 9/33 notes: 1. these parameters depend on output loading. specified values are obtained with the output open. 2. these parameters are masured at minimum cycle test. 3. i cc2 (max.) are mesured under the condition of ttl input level. 4. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 5. an initial pause of 200 m s is required after power-up followed by any 8 ras cycles ( dt / oe high) and any 8 sc cycles before proper divice operation is achieved. in the case of using an internal refresh counter, a minimum of 8 cas before ras initialization cycles in stead of 8 ras cycles are required. 6. ac measurements assume t t = 5 ns. 7. ram port outputs are mesured with a load equivalent to 1 ttl load and 100 pf. output reference levels are v oh /v ol = 2.4 v/0.8 v. 8. sam port outputs are measured with a load equivalent to 1 ttl load and 30 pf. output reference levels are v oh /v ol = 2.0 v/0.8 v. 9. t off (max.), t oez (max.), t sdz (max.) and t sez (max.) difine the time at which the outputs achieve the open circuit condition and are not reference to output voltage levels. 10. either t rch or t rrh must be satisfied for a read cycle. 11. these parameters are referenced to cas leading edge of early write cycles and to wb / we leading edge in oe controlled write cycles and read modify write cycles. 12. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle, and the data out pin will remain open circuit (high impedance) throughout the entire cycle : if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.) the cycle is a read-write cycle and the data out will contain data read from the selected cell : if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indterminate. 13. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only : if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 14. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only : if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 15. input levels at the ac parameter measurement are 3.0 v/0 v. 16. stresses greater than those listed under absolute maximum ratings may cause permenent damege to the device. 17. all voltages are referenced to v ss .
? semiconductor msm54c864 10/33 timing waveform read cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe in out w1/io1 - w8/io8 v ih v il C C v ih v il e e v ih v il e e v ih v il e e v ih v il e e v ih v il e e v oh v ol e e t rc t ras t rp t ar t csh t crp t rcd t rsh t cpn t cas t rad t ral t asr t rah t asc t cah row address column address t rcs t rch t rrh t roh t ths t thh t oea t dzo t cac t aa t rac t off t oez open valid data-out
? semiconductor msm54c864 11/33 *1 wb/we 0 1 w1/io1 - w8/io8 wm1 data don? care cycle write per bit normal write wm1 data: 0: write disable 1: write enable write cycle (early write) "h" or "l" ras cas a0 - a7 wb / we dt / oe in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t cpn t rad t ral t asr t rah t asc t cah row address column address t wsr t rwh t wcs t wch t wp t wcr t cwl t rwl t ths t thh t ms t mh t ds t dh wm1 data valid data-in t dhr open *1
? semiconductor msm54c864 12/33 *1 wb/we 0 1 w1/io1 - w8/io8 wm1 data don? care cycle write per bit normal write wm1 data: 0: write disable 1: write enable write cycle ( oe controlled write) "h" or "l" ras cas a0 - a7 wb / we dt / oe in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t ras t rp t ar t csh t crp t rcd t rsh t cpn t cas t rad t ral t asr t rah t asc t cah row address column address t cwl t rwl t wp t wsr t rwh *1 t wcr t oeh t ths t ms t mh t ds t dh wm1 data valid data-in t dhr open
? semiconductor msm54c864 13/33 *1 wb/we 0 1 w1/io1 - w8/io8 wm1 data don? care cycle write per bit normal write wm1 data: 0: write disable 1: write enable read modify write cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rwc t ras t rp t ar t csh t crp t rcd t rsh t cpn t rad t asr t rah t asc t cah row address column address t wsr t rwh t rcs t cwd t cwl t rwl t wp *1 t awd t rwd t ths t thh t oeh t dzc t ms t mh t dzo t oed t ds t dh wm1 data valid data-in t oea t cac t aa t rac t oez open valid data-out t cas
? semiconductor msm54c864 14/33 fast page mode read cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rasp t rp t ar t pc t crp t rcd t cas t cp t cas t cp t rsh t cas t cpn t rad t csh t asr t rah t asc t cah t asc t cah t ral t asc t cah row address column address 1 column address 2 column address n t rcs t rch t rcs t rch t rcs t rch t rrh t ths t thh t dzo t cpa t cpa t oea t cac t aa t rac t off t oez t oea t cac t aa t off t oez t oea t cac t aa t off t oez open data-out 1 data-out 2 data-out n
? semiconductor msm54c864 15/33 *1 wb/we 0 1 w1/io1 - w8/io8 wm1 data don? care cycle write per bit normal write wm1 data: 0: write disable 1: write enable fast page mode write cycle (early write) "h" or "l" ras cas a0 - a7 wb / we dt / oe in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rasp t rp t ar t pc t crp t rcd t cas t cp t cas t cp t cas t rsh t cpn t rad t csh t asr t rah t asc t cah t asc t cah t asc t ral t cah row address column address 1 column address 2 column address n t wcr t wsr t rwh t wcs t wch t wp t wcs t wch t wp t wcs t wch t wp t ths t thh t cwl t cwl t cwl t rwl t mh t ms t ds t dh t ds t dh t ds t dh t dhr wm1 data data-in 1 data-in 2 data-in n open *1
? semiconductor msm54c864 16/33 *1 wb/we 0 1 w1/io1 - w8/io8 wm1 data don? care cycle write per bit normal write wm1 data: 0: write disable 1: write enable fast page mode read modify write cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe in out w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rasp t rp t ar t csh t prwc t rsh t rcd t cas t cp t cas t cp t cas t asc t asr t rah t cah t cwl t asc t cah t cwl t asc t cah t cwl t rwl row address column address 1 column address 2 column address n t rwh t wsr t wp t wp t wp *1 t cwd t cwd t cwd t rwd t ths t thh t mh t ms t dzo t dzc t ds t oed t dh t dzo t dzc t oed t ds t dh t dzo t dzc t ds t oed t dh wm1 data data- in 1 data- in 2 data- in n t oea t cac t aa t rac t oez t oea t cac t aa t oez t oea t cac t oez t aa data- out 1 data- out 2 data- out n
? semiconductor msm54c864 17/33 "h" or "l" ras cas a0 - a7 wb / we dt / oe w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol e e t rc t ras t rp t crp t rpc t crp t asr t rah row address t ths t thh open ras only refresh cycle
? semiconductor msm54c864 18/33 "h" or "l" ras cas wb / we dt / oe w1/io1 - w8/io8 v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rp t rc t rp t ras t rpc t csr t cpn t chr t off open note: a0 - a7 = don't care ("h" or "l") cas before ras refresh cycle
? semiconductor msm54c864 19/33 "h" or "l" ras cas a0 - a7 wb / we dt / oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C t rc t rc t ras t ar t rp t ras t rp t crp t rcd t rsh t chr t cpn t rad t ral t asr t rah t asc t cah row address column address t rcs t rrh t wsr t rwh t ths t thh t roh t oez t off t oea t cac t aa t off t oez valid data-out w1/io1 - w8/io8 hidden refresh cycle
? semiconductor msm54c864 20/33 read transfer cycle (previous transfer is write transfer cycle) "h" or "l" ras cas a0 - a7 wb / we dt / oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C w1/io1 - w8/io8 v oh v ol e e sc v ih v il e e in v ih v il e e out v oh v ol e e sio1 - sio8 t rc t ras t rp t ar t csh t crp t rcd t rsh t cpn t cas t asr t rah t rad t asc t cah t ral row address sam start address a0 - a7: tap t wsr t rwh t trp t tls t tlh t tp t off t rsd t csd t srs t sc t tsd t scc t scp t sc t scp inhibit rising transient t sds t sdh t szs valid data-in t sca t soh valid data-out note: se = v il
? semiconductor msm54c864 21/33 real time read transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C w1/io1 - w8/io8 v oh v ol C C sc v ih v il C C in v ih v il C C out v oh v ol C C sio1 - sio8 note: se = v il t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t cpn t rad t asr t rah t asc t cah t ral row address sam start address a0 - a7: tap t wsr t rwh t ath t cth t trp t tls t rth t tp t off t scc t sc t scp t tsl t tsd t sca t soh open t sca t soh valid data-out valid data-out valid data-out valid data-out valid data-out previous row data new row data
? semiconductor msm54c864 22/33 pseudo write transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C sc v ih v il C C sio1 - sio8 v oh v ol e e w1/io1 - w8/io8 v oh v ol e e out in v ih v il e e se v ih v il C C t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t cpn t asr t rah t rad t asc t ral t cah row address sam start address a0 - a7: tap t wsr t rwh t tls t tlh t off open t srd t scc t scp t sc t scp t srs inhibit rising transient t sc t esr t reh t sws t sdd t sdz t sez t sds t sdh valid data-in t sca valid data-out valid data-out open t soh serial input data serial input data
? semiconductor msm54c864 23/33 write transfer cycle "h" or "l" ras cas a0 - a7 wb / we dt / oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C v ih v il C C sc v ih v il C C sio1 - sio8 v oh v ol C C w1/io1 - w8/io8 v oh v ol C C out in v ih v il C C se v ih v il C C t rc t ras t rp t ar t crp t csh t rcd t rsh t cas t cpn t rad t asr t rah t asc t ral t cah row address sam start address a0 - a7: tap t wsr t rwh t tls t tlh t ms t off t mh wm1 data open t srd t scc t scp t sc t scp t srs inhibit rising transient t sc t esr t reh t sws t sds t sdh valid data-in t sds t sdh valid data-in valid data-in open previous row data new row data wm1 data: 0: transfer disable 1: transfer enable
? semiconductor msm54c864 24/33 "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C note: se = v il v oh v ol e e sio1 - sio8 t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t scp t scp t scp t scp t scp t scp t sca t sca t sca t sca t sca t soh t soh t soh t soh t soh valid data-out valid data-out valid data-out valid data-out valid data-out valid data-out serial read cycle ( se = v il ) serial read cycle ( se controlled outputs) "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C se v ih v il C C in out v ih v il C C v oh v ol C C sio1 - sio8 t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t scp t scp t scp t scp t scp t scp t sep t sze t sca t soh t sez t sea t sca t sca t soh t sca t soh open valid data-out valid data-out valid data-out valid data-out valid data-out
? semiconductor msm54c864 25/33 "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C note: se = v il v ih v il e e sio1 - sio8 t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t sdh t sdh t sdh t sdh t sdh t scp t scp t scp t scp t scp t scp t sds t sds t sds t sds t sds valid data-in valid data-in valid data-in valid data-in valid data-in serial write cycle ( se = v il ) serial write cycle ( se controlled inputs) "h" or "l" ras dt / oe v ih v il C C v ih v il C C sc v ih v il C C in out v ih v il C C v oh v ol C C sio1 - sio8 v ih v il C C se t ths t thh t scc t scc t scc t scc t scc t sc t sc t sc t sc t sc t scp t scp t scp t scp t scp t scp t swih t swih t sws t swh t sep t sws t swh t sep t sws t swh t swis t se t sds t sdh t sds t sdh t se t swis t se t sds t sdh valid data-in valid data-in valid data-in open
? semiconductor msm54c864 26/33 pin function address input : a0 - a7 the 16 address bits decode an 8-bit location out of the 65,536 locations in the msm54c864 memory array. the address bits are multiplexed to 8 address input pins (a0 to a7) as standard dram. eight row address bits are latched at the falling edge of ras . the following eight column address bits are latched at the falling edge of cas . row address strobe : ras ras is a basic a ram control input signal. the ram port is in standby mode when the ras level is high. as the standard drams ras signal function, ras is the control input that latches the row address bits are a random access cycle begins at the falling edge of ras . in addition to the conventional ram signal functions, the level of the input signals, cas , dt / oe , wb / we , and se , at the falling edge of ras , determines the msm54c864 operation modes. column address strobe : cas as the standard drams cas signal function, cas is the control input signal that latches the column address input and acts as an ram port output enable signal. data transfer / output enable : dt / oe dt / oe is also a control input signal having multiple functions. as the standard drams oe signal function, dt / oe is used as an output enable control when dt / oe is high at the falling edge of ras . in addition to the conventional oe signal function, a data transfer operation is started between the ram port and the sam port when the dt / oe is low at the falling edge of ras . write-per-bit / write enable : wb / we wb / we is a control input signal having multiple functions. as the standard drams we signal function, it is used to write data into the memory array on the ram port when wb / we is high at the falling edge of ras . in addition to the conventional we signal function, the wb / we determines the write-per-bit function when wb / we is low at the falling edge of ras , during ram port operations. the wb / we also determines the direction of data transfer between the ram and sam. when wb / we is high at the falling edge of ras , the data is transferred from ram to sam (read transfer). when wb / we is low at the falling edge of ras , the data is transferred from sam to ram (write transfer).
? semiconductor msm54c864 27/33 write mask data / data input and mask data : w1 / io1 - w8 / io8 w1/ io1 to w8 / io8 have the functions of both input/output and a control input signal. as the standard drams i/o pins, input data on the w1/io1 to w8/io8 are written into the ram port during the write cycle. the input data is latched at the falling edge of either cas or wb / we , whichever occurs later. the ram data out buffers, which will output read data from the w1/io1 to w8 /io8 pins, become low impedance state after the specified access times from ras , cas , dt / oe and column address are satisfied and the output data will remain vaild as long as cas and dt / oe are kept low. the outputs will return to the high-impedance state at the rising edge of either cas or dt / oe , whichever occurs earlier. in addition to the conventional i/o functions, the w1/io1 to w8/io8 have the funnction to set the mask data, which select mask input pins out of eight input pins, w1/ io1 to w8/io8, at the falling edge of ras . data is written in to the dram on data lines where the write-mask data is a logic 1. writing is inhibited on data lines where the write-mask data is a logic 0. the write- mask data is valid for only one cycle. serial clock : sc sc is a main serial cycle contorol input signal. all operations of the sam port are synchronized with the serial clock sc. data is shifted in or out of the sam registers at the rising edge of sc. in a serial read, the output data becomes valid on the sio pins after the maximum specified serial access time t sca from the rising edge of sc. the serial lock sc also increments the 8 bits serial pointer which is used to select the sam address. the pointer address is incremented in a wrap-around mode to select sequential locations after the setting location which is determined by the column address in the read transfer cycle. when the pointer reaches the most significant address location (decimal 255), the next sc clock will place it at the least significant address location (decimal 0). the serial clock sc must be held data constant v ih or v il level during read/pseudo write/write transfer operations and should not be clocked while the sam port is in the standby mode to prevent the sam pointer from being incremented. sam start address data must not be read more than two times: do not input successive sc clocks more than 257. serial enable : se the se is a serial access enable control and serial read/write control input signal. in a serial read cycle, se is used as an output control. in a serial write cycle, se is used as a write enable control. when se is high, serial access is disable, however, the serial address pointer location is still incremented when sc is clocked even when se is high. serial input / output : sio1 - sio8 serial input/output mode is determined by the most recent read, write or pseudo write transfer cycle. when a read transfer cycle is performed, the sam port is in the output mode. when a write or pseudo write transfer cycle is performed, the sam port is switched from output mode to input mode.
? semiconductor msm54c864 28/33 ram port operation fast page mode cycle fast page mode allows data to be transferred into or out multiple column locations of the same row by performing multiple cas cycle during a single active ras cycle. during a fast page cycle, the ras signal may be maintained active for a period up to 100 m seconds. for the initial fast page mode access, the output data is valid after the specified access times from ras , cas , column address and dt / oe . for all subsequent fast page mode read operations, the output data is valid after the specified access times from cas , column address and dt / oe . when the write-per-bit function is enabled, the mask data latched at the falling edge of ras is maintained throughout the fast page mode write or read-modify-write cycle. ras -only refresh the data is the dram requires periodic refreshing to prevent data loss. refreshing is accomplished by performing a memory cycle at each of the 256 rows in the dram array within the specified 4 ms refresh period. although any normal memory cycle will perform the refresh operation, this function is most easily accomplished with ras -only cycle. cas before ras refresh the msm54c864-js/zs also offers an internal-refresh function. when cas is held low for a specified period (t csr ) before ras goes low, an internal refresh address counter and on-chip refresh control clock generators are enabled and an internal refresh operation takes place. when the refresh operation is completed, the internal refresh address counter is automatically incremented in preparation for the next cas -before- ras cycle. for successive cas -before- ras refresh cycle, cas can remain low while cycling ras . hidden refresh a hidden refresh is a cas -before- ras refresh performed by holding cas low from a previous read cycle. this allows for the output data from the previous memory cycle to remain valid while performing a refresh. the internal refresh address counter provides the address and the refresh is accomplished by cycling ras after the specified ras -precharge period. write-per-bit function the write-per-bit selectively controls the internal write-enable circuits of the ram port. write- per-bit is enabled when wb / we held low at the falling edge of ras in a random write operation. also, at the falling edge of ras , the mask data on the wi/ioi pins are latched into a write mask register. the write mask data must be presented at the wi/ioi pins at every falling edge of ras . a 0 on any of the wi/ioi pins will disable the corresponding write circuits and new data will not be written into the ram. a 1 on any of the wi/ioi pins will enable the corresponding write circuits and new data will be written into the ram.
? semiconductor msm54c864 29/33 data transfer operation the msm54c864 features an internal data transfer capability between ram and the sam. during a transfer cycle, 256 words by 8 bits of data can be loaded from ram to sam (read transfer) or from sam to ram (write trasfer). the msm54c864 supports three types of transfer operations: read transfer, write transfer and pseudo write transfer. data transfer operations between ram and sam are invoked by holding the dt / oe signal low at the falling edge of ras , the type of data transfer operation is determined by the state of cas , wb / we and se latched at the falling edge of ras . during data transfer operations, the sam port is switched from input to output mode (read transfer) or output to input mode (write transfer/pseudo write trasfer). during a data transfer cycle, the row a0-a7 select one of the 256 rows of the memory array to or from which data will be transferred and the column address a0-a7 select one of the tap locations in the serial register. the selected tap location is the start position in the sam port from which the first serial data will be read out during the subsequent serial read cycle or the start position in the sam port into which the first serial data will be written during the subsequent serial write cycle. read transfer cycle a read transfer consists of loading a selected row of data from the ram array into the sam register. a read transfer is invoked by holding cas high, dt / oe low and wb / we high at the falling edge of ras . the row address selected at the falling edge of ras determines the ram row to be transferred into the sam. the transfer cycle is completed at the rising edge of dt / oe . when the transfer is completed, the sam port is set into the output mode. in a read/real time read transfer of a new row of data is completed at the rising edge of dt / oe and this data becomes valid on the sio lines after the specified access time t sca from the rising edge of the subsequent serial clock (sc) cycle. the start address of the serial pointer of the sam is determined by the column address selected at the falling edge of cas . in a read transfer cycle preceded by a write transfer cycle, the sc clock must be held at a constant v il or v ih , after the sc high time has been satisfied. a rising edge of the sc clock must not occur until after the specified delay t tsd from the rising edge of dt / oe . in a real time read transfer cycle (which is perceded by another read transfer cycle), the previous row data appears on the sio lines until the dt / oe signal goes high and the serial access time t sca for the following serial clock is satisfied. this feature allows for the first bit of the new row of data to appear on the serial output as soon as the last bit of the previous row has been strobed without any timing loss. to make this continuous data flow possible, the rising edge of dt / oe must be synchronized with ras , cas and the subsequent rising edge of sc (t rth , t cth , and t tsl /t tsd must be satisfied). the timing restriction t tsl /t tsd are 5 ns min./10 ns min..
? semiconductor msm54c864 30/33 write transfer cycle a write transfer cycle transfers the contents of the sam register into a selected row of the ram array. if the sam data to be transferred must first be loaded through the sam port, a pseudo write transfer operation must precede the write transfer cycles. data transferred to sam by read transfer cycle can be written to other address of ram by write transfer cycle. a write transfer is invoked by holding cas low, wb / we low and se low at the falling edge of ras . the row address selected at the falling edge of ras determines the ram row address into which the data will be transferred. the column address selected at the falling edge of cas determines the start address of the serial pointer of the sam. after the writetransfer is completed, the sio lines are set in the input mode so that serial data synchronized with the sc clock can be loaded. when consecutive write transfer operations are performed, new data must not be written into the serial register until the ras cycle of the preceding write transfer is completed. consequently, the sc clock must be held at a constant v il or v ih during the ras cycle. a rising edge of the sc clock is only allowed after the specified delay t srd from the rising edge of ras , at which time a new row of data can be written in the serial register. pseudo write transfer cycle a pseudo write transfer cycle must be performed before loading data into the serial register after a read transfer operation has been excuted. the only purpose of a pseudo write transfer is to change the sam port mode from output mode to input mode (a data transfer from sam to ram does not occur). after the serial register is loaded with new data, a write transfer cycle must be performed to transfer the data from sam to ram. a pseudo write transfer is invoked by holding cas high, dt/oe low, wb / we low and se high at the falling edge of ras . the timing conditions are the same as the one for the write transfer cycle except for the state of se at the falling edge of ras . transfer operation without cas during all transfer cycles, the cas input clock must be cycled, so that the column address are latched at the falling edge of cas , to set the sam tap location. if cas was maintained at a constant high level during a transfer cycle, the sam pointer location would be undifined. therefore a transfer cycle with cas held high is not allowed. normal read transfer cycle after normal read transfer cycle another read transfer may be performed following the read transfer provided that a minimum delay of 30 ns from the rising edge of the first clock sc is satisfied.
? semiconductor msm54c864 31/33 power-up power must be applied to the ras and dt / oe input signals to pull them high before or at the same time as the v cc supply is turned on. after power-up, a pause of 200 m seconds (minimum) is required with ras and dt / oe held high. after the pause, a minimum of 8 ras and 8 sc dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. during the initialization period, the dt / oe signal must be held high. if the internal refresh counter is used, a minimum 8 cas -before- ras initialization cycles are required instead of 8 ras cycle. initial state after power-up when power is achieved with ras , cas , dt / oe and wb / we held high the internal state of the msm54c864 is automatically set as follows. sam port > input mode write mask register > write mode tap pointer > invalid however, the initial state can not be guaranteed for various power-up conditions and input signal levels. therefore, it is recommended that the initial state be set after the initialization of the device is performed (200 m seconds pause followed by a minimum of 8 ras cycles and 8 sc cycles) and before valid operations begin.
? semiconductor msm54c864 32/33 (unit : mm) package dimensions zip40-p-475-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 3.46 typ. mirror finish
? semiconductor msm54c864 33/33 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj40-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.70 typ. mirror finish

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